The present invention relates to a dual speed hub, and more particularly to such a dual speed hub in which a CPU (for example: RISC) periodically sends a test packet through a first MAC, a first hub, a switch and a second hub to a second MAC, then checks the receiving condition so as to determine the normality of the function of the switch, and provides a warning signal to a network management system when the switch is judged abnormal, informing the network manager to repair the switch. The invention relates also to such a dual speed hub redundant switching method.
In recent years, computer networks have been intensively used in different fields. Following the fast development of modern computer technology, the data transmission speed in networks has become more and more fast. For example, the packet transmission speed in an ethernet has been greatly improved from the early 10 Mega bit per second to the current 100 Mega bit per second. Because of quick packet transmission speed, conventional hubs of speed at 10 Mega bit per second are not practical for use in network equipment of speed at 100 Mega bit per second. In order to meet the requirement of ethernet equipment, network system suppliers must provide hubs that can simultaneously receive and transmit packet data at the speed of 10 Mega bit per second as well as at the speed of 100 Mega bit per second so that packet data can be transmitted between different networks accurately. These hubs are commonly called "dual speed hubs".
Regular dual speed hubs include two types, namely the standard dual speed hubs, and the intelligent dual speed hubs. FIG. 1 illustrates a prior art standard dual speed hub 1, which comprises a switch 11, a first hub 12 of speed at 10 Mega bit per second, and a second hub 13 of speed at 100 Mega bit per second. The first hub 12 and the second hub 13 are respectively connected to the transceivers (not shown) of a plurality of I/O ports 14 at the dual speed hub 1. When the transceiver of one I/O port 14 receives a series of packet data from a network apparatus connected thereto, it immediately detects the transmission speed of the network apparatus from which the series of packet data is received, and then transmits the received series of through the first hub 12 or the second hub 13 to another or other I/O ports 14 subject to the transmitting speed detected. Therefore, packet data can be transmitted from the network apparatus at one I/O port to the network apparatus at another I/O port through the first hub 12 or the second hub 13 by means of the control of the switch 11. FIG. 2 illustrates a prior art intelligent dual speed hub 2, which comprises a switch 21, a first hub 22 of speed at 10 Mega bit per second, a second hub 23 of speed at 100 Mega bit per second, a CPU 24, and a MAC (media access control) 25 of speed at 100 Mega bit per second. The CPU 24 reads MIB (management information base) from the chips of the hubs 22,23, and sends network management packets through the MAC 25 to network apparatus of speed at 100 Mega bit per second or through the switch 21 to network apparatus of speed at 10 Mega bit per second subject to the traffic condition in MIB.
In either of the aforesaid two types of dual speed hubs, if the switch is out of function, packet data cannot be normally transmitted between network apparatus of different transmitting speeds, and the user cannot know the malfunction of the dual speed.
Further, in a pile-up dual speed hub architecture, as shown in FIG. 3, the first hubs 32 of speed at 100 Mega bit per second and the second hubs 33 of speed at 10 Mega bit per second of the dual speed hubs 31 are respectively connected in series, and each dual speed hub 31 has a switch 34 therein for speed adjustment, enabling packet data to be accurately transmitted from one network apparatus to another. However, in this piled-up dual speed hub architecture, only one switch 34 is allowed to be started. When the switch 34 of one dual speed hub 31 is started, the switches 34 of the other dual speed hubs 31 must be turned off. If two or more switches 34 are simultaneously started, the switches 34 will form a loop, causing the network system unable to function well. Because the CPU 35 in this pile-up dual speed hub architecture is simply in charge of network management work, it cannot recognize and judge a malfunction of the switch 34 of the respective dual speed hub 31. If the started switch 34 is out of function, the user cannot know the reason of the malfunction of the system, and packet data transmitted in network apparatus at different speeds cannot be exchanged normally through the pile-up dual speed hub architecture.